The AXI protocol has several key features that are designed to improve bandwidth and latency of data transfers and transactions, as you can see here:
AXI supports two different sets of channels, one for write operations, and one for read operations. Having two independent sets of channel helps to improve the bandwidth performances of the interfaces. This is because read and write operations can happen at the same time.
AXI allows for multiple outstanding addresses. This means that a master can issue transactions without waiting for earlier transactions to complete. This can improve system performance because it enables parallel processing of transactions.
With AXI, there is no strict timing relationship between the address and data operations. This means that, for example, a master could issue a write address on the Write Address channel, but there is no time requirement for when the master has to provide the corresponding data to write on the Write Data channel.
For any burst that is made up of data transfers wider than one byte, the first bytes accessed can be unaligned with the natural address boundary. For example, a 32-bit data packet that starts at a byte address of 0x1002 is not aligned to the natural 32-bit address boundary.
Out-of-order transaction completion is possible with AXI. The AXI protocol includes transaction identifiers, and there is no restriction on the completion of transactions with different ID values,
This means that a single physical port can support out-of-order transactions by acting as several logical ports, each of which handles its transactions in order.
AXI masters only issue the starting address for the first transfer. For any following transfers, the slave will calculate the next transfer address based on the burst type.